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Overclocking Failure Modes

October 15, 2017

Using my simple two chip circuit, I wanted to investigate what happened when an 180x ran over its clock limits. I tried my oldest chip, an 1802CD and a newer 1802ACE.

I was running a program equivalent to the following;

0000 LBR FF03
FF03 LBR 0000

This was all actually in the first 6 bytes of an NVRAM with all except the first 3 address lines pulled low.

The reason for this code was to force the 1802 to run in two pages alternately because there was reason to believe that getting the high order address byte correct could be an early failure point.

The first three images show the 1802CD running at 2 and 4 MHz and failing at 6.  In the 2 and 4 MHz cases, keying on the TPAs, you see the init cycle then fetch from 0000, execute 0001, execute 0002, fetch FF03, execute FF04, execute FF05.

17-10-14 CDP1802CD 6MHz zoom

At 6 MHZ it is going through the motions of fetch/execute but i don’t think it’s doing anything sensible. The first fetch is from something like xxxxx000xxxxx111, the subsequent execute reads something like xxxxx000xxxxx001 then it might be trying to fetch from xxxxx010xxxxx111 but the high address is gone before the TPA negative edge.  I think it has just lost it’s sh*t.  Presumably there are a whole bunch of things going on in the chip which are keyed off clock pulses and each with its own calculus of rise and fall setup and hold times. As long as the clock pulses are reasonably far apart it all works but if you crowd them: chaos ensues.

It should be noted that this 40 year old chip has a maximum clock frequency of 2.5Mhz at 5V so it’s a testament to engineering conservatism that it holds together at 4MHz. There still could be a bunch of failures that don’t show up in this simple test but I know from earlier experiments that this chip will execute arbitrary code properly at 4MHz.

Turning to a later version of the chip, the CDP1802ACE is rated for 3.2 MHz at 5V.  In this simple circuit and test it runs fine at 12 MHz and fails at 16 MHz(I don’t have an intermediate frequency resonator). The image below shows it in at 16MHz – it is doing fetch/execute but the address is stuck at xxxxx000xxxxx110. It’s worth noting that even here the high and low addresses are on the bus correctly with respect to TPA.

17-10-14 CDP1202ACE 16mhz
below for the record is the same test at 12MHz which looks fine to me. I have not yet tried this chip with real code in a real circuit.
17-10-14 CDP1202ACE 12mhz

One other learning in passing: The /MRD line is low for >400 ns so there’s just no risk that i would ever oveerun the NVRAM which has a response time of 45 ns.

Also, I can see the extraordinarily tight timing of the high address byte availability at these higher frequencies. The image below shows a fetch where the CPU is going from page 0 to say page FF. The high address lines come up well before TPA but they stay up only for 41 ns after TPA drops. This is enough time for a fast latch to capture it but not a ton more.
17-10-15 TPA1802
The 1806ACEs timing is a bit different than the 1802’s but not in this area. The high address is available for less time overall but the same time after the fall of TPA(which is when you have to latch it)
17-10-15 TPA1806
Also, the 1806 simply will not synch with a 16MHz resonator – it went to around 4-5MHz.

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