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Well Heck – The Way Out of Bizarro World

July 1, 2017

17-07-01 bizarroFor several days I’ve been batting my head against a really odd problem with the Olduino.  With a ROM mounted and addressed at 0x8000 it seemed like I could not pass a pointer to the ROM to a subroutine even if I never referenced the address pointed to. I could accept that there was some problem where accessing the ROM would screw up but I couldn’t figure out where the access was happening.

It turns out the answer is in two parts:

17-06-30 A15First, the memory enabling circuit in the REV G membership card is just way too slow for my system.  It’s a single transistor that inverts A15. At 4 mhz the A15 signal goes high for 2 uS but the inverted signal goes low for almost 8 uS! Both memories are on the bus for several instruction times and hilarity ensues. This is a well known problem but not one i had noticed until it bit me.

17-07-01 mpm201Second, the d*mned 1802 systematically outputs the contents of a register on the address bus whenever you access it! In the table above it shows that the instructions that access the registers (GLO, PLO etc) drive the address bus with the register contents. After 40 years of working with the 1802 I DID NOT KNOW THIS! The 1802 does not assert /MRD or /MWR during these cycles so in theory no harm done but with the ROM enable being stretched, it was still active when the next instruction executed.

In later versions of the membership card schematic the enable circuit is changed a couple of times. If I don’t just give up on the ROM I may adapt one of the fixes or I might try to fit in an inverter.  Maybe one of the little logic single-gate chips in an SOT-23 package.

17-07-01 single gate

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