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Double Oops – Back To the Ghetto!

January 18, 2016

I forgot, programming the attiny that it is supposed to generate the complement of the interrupt signal on a second input pin so the Z80 can tell the source of the interrupt.  No biggie but it means reattaching the programming wires.

Actually though, I wonder why i need the complement.  It’s just a test in the monitor code and i could just as easily test for a 0 as a 1. But, life is short and the monitor code is long – I’ll produce the complement signal.

I found attachment points for each of the attiny’s programming pins except pin 1.  I put a right angle header on that.  It’s messy but if i ever get this right i can clip it off. Doing this I notice I hadn’t hooked up reset to the attiny so i got that as well. The attiny10 programming pins are connected as 1(tpidata/pb0) – via the new header, 3(tpiclk/pb1) – via IN6, 6(reset) – avail at reset.

16-01-17-2 ghetto2

 * tiny10_msec_with_complement.asm
 *  Created: 1/13/2016 3:33:28 PM
 *   Author: bill
 * issues a 25us LOW pulse on pb2 every 1 ms
;16-01-17 adding complemented output on PB1

.DEVICE ATtiny10

; variables for 975 us delay
.EQU delayMult2 = 230; //was 0xff - outer loop
.EQU delayMult3 = 10;//was 0x0f - inner loop
; variables for 25 us delay
.EQU delay25Mult3 = 61;//was 0x0f

.EQU INTOFF = 1<<PB2	;PB2 HIGH, PB1 LOW - no Z80 interrupt & no flag on IN6
.EQU INTON =  1<<PB1	;PB2 low, PB1 high - causes Z80 interrupt & flag on IN6
.CSEG ; code section
.ORG $0000 ; the starting address
	; set up the stack
	ldi r16, high(RAMEND)
	out SPH, r16
	ldi r16, low(RAMEND)
	out SPL, r16
	; set clock divider
	ldi r16, 0x00 ; clock divided by 1
	ldi r17, 0xD8 ; the key for CCP
	out CCP, r17 ; Configuration Change Protection, allows protected changes
	out CLKPSR, r16 ; sets the clock divider

	; initialize port
	ldi r16, INTON+INTOFF ; sets pins 3 and 4 (PB1 and PB2) to output
	out DDRB, r16 ; data direction
	ldi r16, INTOFF ; no interrupt
	out PORTB, r16
	; nop for sync
	rcall delay	;startup delay 1ms

	; issue interrupt and delay 25us
	ldi r16, INTON
	out PORTB, r16
	rcall delay25
	; release interrupt and delay 975us
	ldi r16, INTOFF
	out PORTB, r16
	rcall delay
	rjmp loop

	; not really needed, but keep r16-r18
	push r17
	push r18
	ldi r17, delayMult2
	ldi r18, delayMult3

	; start delay loop
	ldi  r18,delaymult3
	subi r18,1
	brne delayLoopInner

	subi r17,1
	brne delayLoopOuter
	; end delay loop

	pop r18
	pop r17

	; not really needed, but keep r18
	push r18
	ldi r18, delay25Mult3

	; start delay loop
	subi r18, 1 ; ubtract 1
	brne delay25Loop ; while r18 is not 0, loop
	; end delay loop

	pop r18


From → Olduino/Z

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