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Millisecond Clock Using Attiny10

January 15, 2016

16-01-15 msec clock

I wanted to use something small to generate my 1khz interrupt for the z80.  On the protoboard I used a through hole attin85 but that’s still pretty bulky.  I put a footprint for an soic part on the new pcb but i also left a footprint for the teeny tiny attiny10.  This is a 6 pin sot23 part, certainly the smallest processor i’ve ever seen.

I got the programming and hookup info from here  and it worked pretty much first time.  I cooked up a little assembly program to issue a 25us LOW on one pin every ms and programmed it.  I didn’t carefully count cycles, just bodged around with delay counts til i got it close.  If I get ambitious some time i’ll do a more careful job. In the gallery below you can see the attiny10 on my fingertip and soldered in place as well as my ghetto programmer.


/*
 * tiny10_msec.asm
 *
 *  Created: 1/13/2016 3:33:28 PM
 *   Author: bill
 * issues a 25us LOW pulse on pb2 every 1 ms
 */ 

.DEVICE ATtiny10

; variables for 975 us delay
.EQU delayMult2 = 230; //was 0xff - outer loop
.EQU delayMult3 = 10;//was 0x0f - inner loop
; variables for 25 us delay
.EQU delay25Mult3 = 61;//was 0x0f

.CSEG ; code section
.ORG $0000 ; the starting address
main:
	; set up the stack
	ldi r16, high(RAMEND)
	out SPH, r16
	ldi r16, low(RAMEND)
	out SPL, r16

	; set clock divider
	ldi r16, 0x00 ; clock divided by 1
	ldi r17, 0xD8 ; the key for CCP
	out CCP, r17 ; Configuration Change Protection, allows protected changes
	out CLKPSR, r16 ; sets the clock divider

	; initialize port
	ldi r16, 1<<PB2 ; sets pin 4 (PB2) to putput
	out DDRB, r16 ; data direction
	ldi r16, 0x00 ; sets all pins low
	out PORTB, r16

	; nop for sync
	nop

loop:
	; turn off and delay 25us
	ldi r16, 0
	out PORTB, r16
	rcall delay25

	; turn on and delay 975us
	ldi r16, (1<<PB2)
	out PORTB, r16
	rcall delay
	rjmp loop

delay:
	; not really needed, but keep r16-r18
	push r17
	push r18

	ldi r17, delayMult2
	ldi r18, delayMult3

	; start delay loop
delayLoopOuter:
	ldi  r18,delaymult3
delayLoopInner:
	subi r18,1
	brne delayLoopInner

	subi r17,1
	brne delayLoopOuter
	; end delay loop

	pop r18
	pop r17
	ret

delay25:
	; not really needed, but keep r18
	push r18

	ldi r18, delay25Mult3

	; start delay loop
delay25Loop:
	subi r18, 1 ; ubtract 1
	brne delay25Loop ; while r18 is not 0, loop
	; end delay loop

	pop r18
	ret

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From → Olduino/Z

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