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PCB Ordered!

December 14, 2015

I want to try to get a PCB done before we take our winter break in florida.  That way i can work on software while i’m there.  My board layout is bigger than it needs to be but hopefully it will work.  The basic components are the TP3465V SPI chip , some the reset and serial circuits, and an ATTINY85 which generates the millisecond clock.  I also left room for a 16 pin dip and, going the other way, an attiny10 – that’s a 6 pin avr that should be able to do the clock function instead of the attiny85.

Seeed takes three-ish weeks for delivery, probably worse over year end holidays but if i get it even as late as jan 25 i can probably assemble it in a few days.

15-12-14 sch 7

15-12-14 brd 7Seeed has a gerber viewer now which is cool. At first I had missed the _tsilk and _bsilk layers in the gerbers and the viewer let me catch the error.

Random things I learned:

  • Here’s how to get eagle to pay attention to a new library
  • The eagle autorouter wouldn’t run the power leads to the sot23 footprint for the attiny10 because the track width would have interfered with other pins.  I hand routed them and hopefully that will be ok.
  • I built my own part for the tp3465v spi chip. painstaking and error prone, i hope i managed it.  Interestingly, if not surprisingly, the .lbr file contains what looks like xml.  Miight not be smart to modify it directly but it might be easy to do some kinds of changes at the text level rather than graphically.
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<pin name="NC1" x="15.24" y="-15.24" visible="off" length="point" direction="nc"/>
<symbol name="T89C51CC02">
<wire x1="-17.78" y1="-22.86" x2="17.78" y2="-22.86" width="0.4064" layer="94"/>
<wire x1="17.78" y1="-22.86" x2="17.78" y2="27.94" width="0.4064" layer="94"/>
<wire x1="17.78" y1="27.94" x2="-17.78" y2="27.94" width="0.4064" layer="94"/>
<wire x1="-17.78" y1="27.94" x2="-17.78" y2="-22.86" width="0.4064" layer="94"/>
<text x="-17.78" y="-25.4" size="1.778" layer="96">&gt;VALUE</text>
<text x="-17.78" y="28.575" size="1.778" layer="95">&gt;NAME</text>
<pin name="A0" x="-22.86" y="-2.54" length="middle"/>
<pin name="A1" x="-22.86" y="-5.08" length="middle"/>
<pin name="AD0" x="-22.86" y="20.32" length="middle"/>
<pin name="AD1" x="-22.86" y="17.78" length="middle" direction="in"/>
<pin name="/RST" x="-22.86" y="25.4" length="middle" direction="in"/>
<pin name="AS/MI" x="22.86" y="20.32" length="middle" rot="R180"/>
<pin name="/MULT-/INT" x="22.86" y="17.78" length="middle" rot="R180"/>
<pin name="CS0" x="22.86" y="12.7" length="middle" direction="out" rot="R180"/>
<pin name="CS1" x="22.86" y="10.16" length="middle" rot="R180"/>
<pin name="CS2" x="22.86" y="7.62" length="middle" rot="R180"/>
<pin name="CS3" x="22.86" y="5.08" length="middle" rot="R180"/>
<pin name="SK" x="22.86" y="-5.08" length="middle" rot="R180"/>
<pin name="SO(MOSI)" x="22.86" y="0" length="middle" rot="R180"/>
<pin name="SI(MISO)" x="22.86" y="-2.54" length="middle" rot="R180"/>
<pin name="CKIN" x="22.86" y="-10.16" length="middle" rot="R180"/>
<pin name="AD2" x="-22.86" y="15.24" length="middle"/>
<pin name="AD3" x="-22.86" y="12.7" length="middle"/>
<pin name="AD4" x="-22.86" y="10.16" length="middle"/>
<pin name="AD5" x="-22.86" y="7.62" length="middle"/>
<pin name="AD6" x="-22.86" y="5.08" length="middle"/>
<pin name="AD7" x="-22.86" y="2.54" length="middle"/>
<pin name="/WR" x="-22.86" y="-20.32" length="middle"/>
<pin name="/RD" x="-22.86" y="-17.78" length="middle"/>
<pin name="VCC" x="22.86" y="25.4" length="middle" direction="pwr" rot="R180"/>
<pin name="VSS" x="22.86" y="-20.32" length="middle" direction="pwr" rot="R180"/>
<pin name="A3" x="-22.86" y="-10.16" length="middle" direction="in"/>
<pin name="A2" x="-22.86" y="-7.62" length="middle" direction="in"/>
<pin name="/CE" x="-22.86" y="-15.24" length="middle" direction="in"/>
<deviceset name="TP3465V" prefix="IC">
<description>&lt;b&gt;Texas Instruments TP3465 Microwire Interface Device&lt;/b&gt;</description>
<gate name="G$1" symbol="T89C51CC02" x="0" y="0"/>
<device name="TIS" package="SO28W">
<connect gate="G$1" pin="/CE" pad="3"/>
<connect gate="G$1" pin="/MULT-/INT" pad="6"/>
<connect gate="G$1" pin="/RD" pad="7"/>
<connect gate="G$1" pin="/RST" pad="19"/>
<connect gate="G$1" pin="/WR" pad="8"/>
<connect gate="G$1" pin="A0" pad="5"/>
<connect gate="G$1" pin="A1" pad="4"/>
<connect gate="G$1" pin="A2" pad="2"/>
<connect gate="G$1" pin="A3" pad="1"/>
<connect gate="G$1" pin="AD0" pad="16"/>
<connect gate="G$1" pin="AD1" pad="15"/>
<connect gate="G$1" pin="AD2" pad="14"/>
<connect gate="G$1" pin="AD3" pad="13"/>
<connect gate="G$1" pin="AD4" pad="12"/>
<connect gate="G$1" pin="AD5" pad="11"/>
<connect gate="G$1" pin="AD6" pad="10"/>
<connect gate="G$1" pin="AD7" pad="9"/>
<connect gate="G$1" pin="AS/MI" pad="20"/>
<connect gate="G$1" pin="CKIN" pad="21"/>
<connect gate="G$1" pin="CS0" pad="28"/>
<connect gate="G$1" pin="CS1" pad="27"/>
<connect gate="G$1" pin="CS2" pad="26"/>
<connect gate="G$1" pin="CS3" pad="25"/>
<connect gate="G$1" pin="SI(MISO)" pad="22"/>
<connect gate="G$1" pin="SK" pad="24"/>
<connect gate="G$1" pin="SO(MOSI)" pad="23"/>
<connect gate="G$1" pin="VCC" pad="17"/>
<connect gate="G$1" pin="VSS" pad="18"/>
<technology name="CA">
<attribute name="MF" value="" constant="no"/>
<attribute name="MPN" value="DIL40/SOIC28ZIFAWM-1" constant="no"/>
<attribute name="OC_FARNELL" value="unknown" constant="no"/>
<attribute name="OC_NEWARK" value="89M9134" constant="no"/>
<technology name="UA">
<attribute name="MF" value="" constant="no"/>
<attribute name="MPN" value="DIL40/SOIC28ZIFAWM-1" constant="no"/>
<attribute name="OC_FARNELL" value="unknown" constant="no"/>
<attribute name="OC_NEWARK" value="89M9134" constant="no"/>
<device name="SIS" package="PLCC28">
<connect gate="G$1" pin="/CE" pad="3"/>
<connect gate="G$1" pin="/MULT-/INT" pad="6"/>
<connect gate="G$1" pin="/RD" pad="7"/>
<connect gate="G$1" pin="/RST" pad="19"/>
<connect gate="G$1" pin="/WR" pad="8"/>
<connect gate="G$1" pin="A0" pad="5"/>
<connect gate="G$1" pin="A1" pad="4"/>
<connect gate="G$1" pin="A2" pad="2"/>
<connect gate="G$1" pin="A3" pad="1"/>
<connect gate="G$1" pin="AD0" pad="16"/>
<connect gate="G$1" pin="AD1" pad="15"/>
<connect gate="G$1" pin="AD2" pad="14"/>
<connect gate="G$1" pin="AD3" pad="13"/>
<connect gate="G$1" pin="AD4" pad="12"/>
<connect gate="G$1" pin="AD5" pad="11"/>
<connect gate="G$1" pin="AD6" pad="10"/>
<connect gate="G$1" pin="AD7" pad="9"/>
<connect gate="G$1" pin="AS/MI" pad="20"/>
<connect gate="G$1" pin="CKIN" pad="21"/>
<connect gate="G$1" pin="CS0" pad="28"/>
<connect gate="G$1" pin="CS1" pad="27"/>
<connect gate="G$1" pin="CS2" pad="26"/>
<connect gate="G$1" pin="CS3" pad="25"/>
<connect gate="G$1" pin="SI(MISO)" pad="22"/>
<connect gate="G$1" pin="SK" pad="24"/>
<connect gate="G$1" pin="SO(MOSI)" pad="23"/>
<connect gate="G$1" pin="VCC" pad="17"/>
<connect gate="G$1" pin="VSS" pad="18"/>
<technology name="CA"/>
<device name="RAT" package="VQFP32">
<connect gate="G$1" pin="/CE" pad="31"/>
<connect gate="G$1" pin="/MULT-/INT" pad="2"/>
<connect gate="G$1" pin="/RD" pad="3"/>
<connect gate="G$1" pin="/RST" pad="17"/>
<connect gate="G$1" pin="/WR" pad="4"/>
<connect gate="G$1" pin="A0" pad="1"/>
<connect gate="G$1" pin="A1" pad="32"/>
<connect gate="G$1" pin="A2" pad="29"/>
<connect gate="G$1" pin="A3" pad="28"/>
<connect gate="G$1" pin="AD0" pad="14"/>
<connect gate="G$1" pin="AD1" pad="13"/>
<connect gate="G$1" pin="AD2" pad="11"/>
<connect gate="G$1" pin="AD3" pad="10"/>
<connect gate="G$1" pin="AD4" pad="9"/>
<connect gate="G$1" pin="AD5" pad="8"/>
<connect gate="G$1" pin="AD6" pad="6"/>
<connect gate="G$1" pin="AD7" pad="5"/>
<connect gate="G$1" pin="AS/MI" pad="19"/>
<connect gate="G$1" pin="CKIN" pad="20"/>
<connect gate="G$1" pin="CS0" pad="27"/>
<connect gate="G$1" pin="CS1" pad="26"/>
<connect gate="G$1" pin="CS2" pad="25"/>
<connect gate="G$1" pin="CS3" pad="24"/>
<connect gate="G$1" pin="SI(MISO)" pad="21"/>
<connect gate="G$1" pin="SK" pad="23"/>
<connect gate="G$1" pin="SO(MOSI)" pad="22"/>
<connect gate="G$1" pin="VCC" pad="15"/>
<connect gate="G$1" pin="VSS" pad="16"/>
<technology name="CA">
<attribute name="MF" value="" constant="no"/>
<attribute name="MPN" value="" constant="no"/>
<attribute name="OC_FARNELL" value="unknown" constant="no"/>
<attribute name="OC_NEWARK" value="unknown" constant="no"/>
<technology name="UA">
<attribute name="MF" value="" constant="no"/>
<attribute name="MPN" value="" constant="no"/>
<attribute name="OC_FARNELL" value="unknown" constant="no"/>
<attribute name="OC_NEWARK" value="unknown" constant="no"/>
<device name="" package="S28">
<connect gate="G$1" pin="/CE" pad="19"/>
<connect gate="G$1" pin="/MULT-/INT" pad="18"/>
<connect gate="G$1" pin="/RD" pad="12"/>
<connect gate="G$1" pin="/RST" pad="22"/>
<connect gate="G$1" pin="/WR" pad="11"/>
<connect gate="G$1" pin="A0" pad="6"/>
<connect gate="G$1" pin="A1" pad="9"/>
<connect gate="G$1" pin="A2" pad="20"/>
<connect gate="G$1" pin="A3" pad="23"/>
<connect gate="G$1" pin="AD0" pad="1"/>
<connect gate="G$1" pin="AD1" pad="2"/>
<connect gate="G$1" pin="AD2" pad="3"/>
<connect gate="G$1" pin="AD3" pad="4"/>
<connect gate="G$1" pin="AD4" pad="5"/>
<connect gate="G$1" pin="AD5" pad="7"/>
<connect gate="G$1" pin="AD6" pad="8"/>
<connect gate="G$1" pin="AD7" pad="10"/>
<connect gate="G$1" pin="AS/MI" pad="21"/>
<connect gate="G$1" pin="CKIN" pad="17"/>
<connect gate="G$1" pin="CS0" pad="24"/>
<connect gate="G$1" pin="CS1" pad="25"/>
<connect gate="G$1" pin="CS2" pad="26"/>
<connect gate="G$1" pin="CS3" pad="27"/>
<connect gate="G$1" pin="SI(MISO)" pad="16"/>
<connect gate="G$1" pin="SK" pad="13"/>
<connect gate="G$1" pin="SO(MOSI)" pad="15"/>
<connect gate="G$1" pin="VCC" pad="28"/>
<connect gate="G$1" pin="VSS" pad="14"/>
<technology name=""/>

From → Olduino/Z

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