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For My Next Trick

September 29, 2015

I’m going to try the logic analyzer on the Z80. I’ll just monitor control and a few address lines and count on knowing the program contents – probably all 0’s to start.

Looking at the timing diagrams it looks like i can usefully monitor as few as /mreq /rd and /m1 for starters – the address bits will be valid on the leading/falling edge of /rd. Oh, I’ll also need /reset. So I’ll have a grand total of 4 address lines to play with.
15-09-29 z80 m1 cycle
15-09-29 z80 mem cycle15-09-29 z80 int cycle

15-09-29 z80 io cycle

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From → Olduino/Z

4 Comments
  1. inaxeon permalink

    Now you’re seeing the frustrations I had trying to do logic analysis. I first started with one these: http://sigrok.org/wiki/Sysclk_LWLA1034

    But even 34 channels was nowhere near enough!

    It’s a bit annoying how few options there are for those who need *lots* of channels on a budget.

  2. Huh, I dream of 34 channels! I remember seeing a huge standalone logic analyzer on your site and being impressed with how hard core you were.

    I looked on eBay and saw something saying it was a LWLA1034 in the $80 range – does that make sense? My Saleae 8 bit cost me over $100. Did the LWLA1034 work well other than the “lack” of channels?

    As it happens, in this instance, with known source code, I was able to puzzle my way though with 4 bits of address and no data!

  3. inaxeon permalink

    Yes the LWLA1034 is pretty budget, probably cheaper than a Salae. I found the LWLA1034 to be OK. I did the first few weeks of analysis on my project with it.

    But quickly got frustrated and bought the Agilent, mine which is fitted with 144 channels (of a ridiculous 360 maximum)

    The vendor software of the LWLA1034 isn’t perfect. I encountered a few bugs while using it but nothing that couldn’t be worked around. It’s supported by the open source sigrok project (Also supports Salae) which in theory should be more stable.

    I mean don’t get me wrong, that Salae looks damn nice. The software looks good, it’s well built too. Ugh, but unfortunately at a maximum of 16 channels it’s just no use to me. Also disappointing that it has no fronted amplifiers so loads the device under test a lot more than my Agilent.

    Interesting to see the bus timing stuff. I’m presently doing some bus timing work on my 8086 arduino (have been writing it on my blog) which is requiring 70 channels. Ayee.

  4. geez – I’ll go look.

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