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Well This Is Awkward – Optimization Ends In Tears

April 15, 2015

The 1802 has a wonderfully simple instruction set.For example hex 50 is a store instruction “STR 0” that puts the value in D wherever register 0 points same for 51…5F. Almost all register instructions are like that EXCEPT for “LDN x” which is hex 0x and means load the byte pointed to by register x UNLESS x is 0! Hex 00 is in fact an IDL instruction that halts the processor. The assembler protects you from yourself and gives an error if you try to “LDN 0”.

I was surprised to see that error message pop up when Iw was assembling a double dabble variant. Looking at the assembly I could, of course, see the offending line

      85/     1AA : (MACRO)             	ldn1 R13,R0	;opt14*
;muledd32cr1.asm(85) LDN1(1): error: invalid register

The problem is coming from the peephole optimizer which saw the compiler emit
ld1 R13,’O’,R0,0
which means load one byte from 0 bytes past R0 and put it in the bottom of R13
LD1 uses an elaborate mechanism to calculate the effective address so where the optimizer sees a zero offset it sticks in an LDN1 instead saving a bunch of instructions. For the moment I’m just compiling without the -O switch so the optimizer doesn’t run but i’ll have to somehow disallow that optimization for R0.

The optimizer rule is below:

	ld1 %1,'O',%2,0
=
	ldn1 %1,%2	;opt14*

I think i can disable it for R0 by preceding it with something like

	ld1 %1,'O',R0,0
=
	ld1 %1,'O',R0,0 ;opt 14 would fail here - comment prevents it triggering

R0 is the last register to be used for variables so it probably doesn’t get used as a pointer very often otherwise i would have seen this error before.

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