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Software PWM VI – Toggle Table Correction

October 11, 2014

I found odd results from the pwm routines yesterday and this morning i tracked them down to a simple error in the pwmstep routine: in the two lines marked ** below I was just assigning to the toggle table instead of or’ing in the values.

void pwmstep(){	//run one step of the software pwm cycle
	PIN4^=toggle[step]; out(4,PIN4); //toggles the bit off if the duty cycle is over
	//printf("dct[0]=%cx, step %d, toggle[%d]=%cx, PIN4=%cx\n",dct[0],step, step, toggle[step],PIN4);
	toggle[step++]=0;
	if (8==step){//if we're done a full pass
		step=0;	//reset the index
	**	toggle[dct[0]]|=1; //set the end of the duty cycle for bit 0 
	**	toggle[dct[1]]|=2; //set the end of the duty cycle for bit 1 
		toggle[0]^=~PIN4; //set up with current state of port4 low bits
		toggle[0]&=0x03; //only the pwm bits are set
	}
}

Now I get nice repeatable results and no interference between the PWM bits. There are still a couple of issues in the logic analyzer trace below:
1) After you change the duty cycle, it takes another full pass thru the toggle table to take effect(you see that below where the first trace does a cycle at 50% then settles to 25% and
2) At the beginning of a run, bit 1, PWMA is going high for two seconds while the 1802 is in reset.
14-10-11 saleae
Item 1 is clearly software but item 2 could be something to do with my circuit for the parallel out which is supposed to tri-state the output latch while the 1802 is reset.
I’m not sure either of these is important because the cycle should be quick and the 1802 doesn’t have to spend that long in reset but both items offend me.

Per the circuit below the parallel port should be tri-stated biy IC3A during that reset period. I did that because I didn’t want the port to be selecting a bunch of SPI devices at the same time. I figured I could pull the bits high or low as needed.
14-08-21 part schematic

In the analyzer trace above, bit 0 had an analog meter on it and bit 1 didn’t. When I moved the meter to bit 1 the 2 second ‘high’ moved to bit 0 so the logic analyzer was pulling the tri-state bits high. I’m just going to go ahead and, if i have to, i’ll use a pulldown resistor.

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