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Tightening up the MOSR timing with the 74165

May 27, 2014

So the whole point of this was to speed up spi communications by allowing a faster clock rate and handling a byte within a single 1802 instruction cycle.  Remember tat the 1802 writes to the shift register with OUT 6.  The AVR sees the N line go high and toggles  the clock 8 times.  If the 1802 comes back before the avr is finished the 8 clocks, we’ll miss or garble a byte.  I had to try a simple experiment to see if I could satisfy the two goals. In the guts of the code for the elec-freaks 2.2″ LCD there’s a routine that clears it. This involves sending 2 bytes of 0’s for each of 240*320 cells. The code looks like this

		"_lcdclearer:\n" 	//fills full lcd with 0's
			"	ldaD R8,240*320/4\n" //#cells  /4
			"	ldi 0\n	dec 2\n	str 2\n" //set up the work area
			"	cpy2 R9,2\n	sex 9\n"	//point a temp reg at it and make that X
		"$$clrloop:\n"		//come back here for more
			"	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n	out 6\n	dec 9\n"	//send 8 0's
			"	dec R8\n"	//decrease counter
			"	glo R8\n	bnz $$clrloop\n" //back for more
			"	ghi R8\n	bnz $$clrloop\n" //til done
			"	inc R2\n"	//release work area
		"	cretn\n");	//and we're done

The line that starts “out 6\n dec 9\n” actually sends out the 0’s and the “dec 9” is partly a filler so i don’t do two out 6’s in a row. With a couple of other changes I changed the X register to be the program counter and changed that line to be “out 6\n db 00\n”. Both those sequences are repeated 8 times for each pass thru the loop.

When I ran the new sequence the time to clear the LCD was cut down from 3.7 to 2.1 seconds and instantaneous transfer rate went from 50,000 to 100,000 bytes/second. More importantly, it showed that the 1802 wouldn’t step on the spi clock by coming back too quickly.

In the sequence below I’m actually sending out 0x55 rather than 0’s so i can make sure the bit pattern is preserved. The 1802 I/O requests are the negative going pulse at the top and you can see that the shifting is finished long before the next request.

The I/O requests are 10us apart now, at 3mhz they’ll be 5us apart and I’ll have to speed up the spi clock to 3-4mhz to keep up.  I’ll also look at shortening the gap between the request pulse and starting the shiftout.  Just running the AVR at 16mhz instead of 8 will probably fix that.

14-05-27 one inst 55

 

There’s a link to a pdf of the schematic below:

14-05-27 olduino_2.0_v5b

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