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demorgans is kicking my *ss

December 31, 2013
CDP1802 I/O logic signals

CDP1802 I/O logic signals

I am working on the all-in-one olduino with the 1802 on the same board with the avr and spi circuits.  This is good because it lets me be right on the 1802 bus instead of having to bodge my way around the membership card’s latches but it means I have to do the decoding more precisely to latch the data and provide it at just the right times.  There are 4 main signals: N1 which addresses the SPI hardware and N2 which addresses the parallel output, /MRD that tells me whether the CPU is reading memory, and TPB which tells me the data from the CPU is valid.  Oh, and there’s /WAIT which is low if the CPU is in load mode.

The targets for the decoding are a 74374 output latch which wants a positive going edge, a 4021 which wants a positive pulse, and a 74595 input shift register which wants a NEGATIVE pulse.  The combination of these is driving me mad.

I have actually done this with the 1802 several times but it is always a brain breaker for some reason.

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