Epiphanies are cheap this week
With a 1mhz or 2mhz clock and the 1802 running at 1.6mhz I need a one instruction delay between succeeding shift register accesses. This is really only noticeable when I want to do a read-after-write to pick up the data that’s been shifted in from miso and that’s only a problem because the outbound shift register reloads whenever IO6 comes high. If I gate that properly so it’s only on a write, I can overlap the read after write by a couple of clock cycles – probably enough at 2mhz to allow a direct read-after-write. If I wanted to be able to do write-after-write, I would need to gate that again with TPB. Next iteration I’ll look at that.