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SPI Epiphany

December 16, 2013

Ever since I started using external shift registers for SPI I’ve been running a two stage clock on two separate pins: SCK is the normal SPI clock – it latches MISO into the 74595 inbound shift register and tells the slave to latch MOSI which is the top bit of the 4021 outbound shift register; SCK2 rises after SCK and does two things: It shifts the bits in the 4021 output register and tells the 74595 to copy its data from its shift register to its storage register from where it can be gated onto the bus by the 1802’s INP 6. There may well have been some peculiar reason why i needed the two stage clock at one point but I don’t think I do now.  The SCK2 signal can be the falling edge of SCK which is what all the spi documentation implies is standard behaviour anyway!

Easy to try this with the clock generator.  And bingo – it works fine with the single stage clock.  At 2 mhz the signals are rock solid and the logic works.  At 4 mhz the 4021 is past its limits and the circuit goes to heck.

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